Single-ended sensing techniques are used in many circuit applications for both memory and logic. Standard memory arrays include a plurality of row lines, often arranged horizontally, a plurality of bit lines, often arranged vertically orientation (e.g., in columns), and a plurality of memory cells, each memory cell being coupled to a unique pair of row and bit lines. A first subset of the memory cells are typically connected to a common row line. Likewise, a second subset of the memory cells, which may include memory cells from the first subset, are typically connected to a common bit line. When a given row line is activated, data states within the memory cells connected to the row line are coupled to the corresponding bit lines; typically, only one memory cell is coupled to its corresponding bit line at a given time.
A bit line is typically shared by a number of memory cells and other circuit elements. The number of memory cells and circuit elements connected to a bit line significantly influences the time it takes for a single memory cell to charge or discharge the bit line, as is required during a read operation. In many cases, the bit line in a memory array is precharged to a power supply voltage of the memory array, which may be VDD, or an alternative voltage level indicative of a logic “1” data state. Alternately, the bit line may be precharged to ground or VSS, or an alternative voltage level indicative of a logic “0” data state. During a read operation of a memory array with the bit line precharged to a logic “1” state, after the bit line is precharged, a programmed logic “0” memory cell actively pulls down the bit line, while a programmed logic “1” memory cell does not drive the bit line down, so that the bit line remains substantially at the precharge voltage level. The resulting voltage level on the bit line can be sensed by a sense amplifier, for example, an inverter. The time it takes for the bit line voltage to reach a switching point of the sense amplifier, when sensing a logic “0” data state, defines the local bit line access time.
Unfortunately, leakage current from the memory cells and/or other circuit elements connected to the bit lines can at least partially discharge the bit lines. When the voltage level of a given bit line has been discharged to below the switching point of the sense amplifier as a result of leakage current, an erroneous logic “0” state will be read. Variations in process, voltage and/or temperature (PVT) conditions to which the memory array is subjected can increase the leakage current, and thereby further exacerbate the logic “0” read error condition in the memory array.